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ICS650-27
Networking Clock Source
Description
The ICS650-27 is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. The ICS650-27 outputs all have zero ppm synthesis error. The ICS650-27 is pin compatible and functionally equivalent to the ICS650-07. It is a performance upgrade and is recommended for all new 3.3V designs. See the MK74CB214, ICS551, and ICS552-01 for non-PLL buffer devices which produce multiple low-skew copies of these output clocks. See the ICS570, ICS9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks.
Features
* Packaged in 20-pin (150 mil) SSOP (QSOP) * Available in Pb (lead) free package * 12.5 MHz or 25 MHz fundamental crystal or clock * * * * * * * * *
input Six output clocks with selectable frequencies SDRAM frequencies of 67, 83, 100, and 133 MHz Buffered crystal reference output Zero ppm synthesis error in all clocks Ideal for PMC-Sierra's ATM switch chips Full CMOS output swing with 25 mA output drive capability at TTL levels Advanced, low-power, sub-micron CMOS process Operating voltage of 3.3 V Industrial temperature only
Block Diagram
VDD 2
CLKA1
ACS1:0 BCS1:0 CCS 2 2 Clock Synthesis and Control Circuitry
/2
CLKA2 CLKB1
/2
CLKB2 CLKC1 CLKC2
X1/ICLK 25 or 12.5 MHz cyrstal or clock X2
Clock Buffer/ Crystal Oscillator 2
REFOUT
OE (all outputs)
GND
MDS 650-27 D Integrated Circuit Systems, Inc.
1
525 Race Street, San Jose, CA 95126
Revision 070505 tel (408) 297-1201
www.icst.com
ICS650-27 Networking Clock Source
Pin Assignment
ASC0 X2 X1/ICLK VDD ASC1 GND CLKC1 CLKC2 CLKB2 CLKB1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 BCS1 BCS0 REFOUT CLKA1 VDD OE GND CLKA2 DC CCS
20-pin (150 mil) SSOP
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Name
ACS0 X2 X1/ICLK VDD ACS1 GND CLKC1 CLKC2 CLKB2 CLKB1 CCS DC CLKA2 GND OE VDD CLKA1 REFOUT BCS0 BCS1
Pin Type
Input Input Input Power Input Power Output Output Output Output Input Output Power Input Power Output Output Input Input
Pin Description
A clock select 0. Selects outputs on CLKA1 and CLKA2 per table on page 3. Crystal connection. Connect to a fundamental crystal or leave unconnected for a clock input. Crystal connection. Connect to a fundamental crystal or clock input. Connect to +3.3 V or 5 V. Must be the same as pin 16. A clock select 1. Selects outputs on CLKA1 and CLKA2 per table on page 3. Internal pull-up. Connect to ground. Output Clock C1. Depends on setting of CCS per table on page 3. Output Clock C2. Depends on setting of CCS per table on page 3. Same as CLKC1. Output Clock B2. Depends on setting of BCS1, 0 per table on page 3. Output Clock B1. Depends on setting of BCS1, 0 per table on page 3. Clock C select pin. Selects outputs on CLKC1 and CLKC2 per table on page 3. Don't connect. Do not connect anything to this pin. Output Clock A2. Depends on setting of ACS1, 0 per table on page 3. Connect to ground. Output enable. Tri-states all outputs when low. Internal pull-up. Connect to +3.3 V or 5 V. Must be the same as pin 4. Output Clock A1. Depends on setting of ACS1, 0 per table on page 3. Buffered reference clock output. Same frequency as crystal or clock input. B clock select 0. Selects outputs on CLKB1 and CLKB2 per table on page 3. B clock select 1. Selects outputs on CLKB1 and CLKB2 per table on page 3. Internal pull-up.
MDS 650-27 D Integrated Circuit Systems, Inc.
2
525 Race Street, San Jose, CA 95126
Revision 070505 tel (408) 297-1201
www.icst.com
ICS650-27 Networking Clock Source
For a 25 MHz fundamental crystal or clock input, the following four tables apply:
A Clocks Select Table (outputs in MHz) ASC1 0 0 0 1 1 1 ASC0 0 M 1 0 M 1 CLKA1 100 Test 75 33.3333 Test 66.6667 CLKA2 off (low) Test off (low) 16.6667 Test 33.3333 B Clocks Select Table (outputs in MHz) BSC1 0 0 0 1 1 1 BSC0 0 M 1 0 M 1 CLKB1 Test 66.6667 100 83.3333 Test 133.3333 CLKB2 Test 33.3333 50 41.6667 Test 66.6667
C Clocks Select Table (outputs in MHz) CCS 0 M 1 CLKC1 125 Test 75 CLKC2 125 Test 75
Reference Output Clock Frequency (in MHz) REFOUT 25
For a 12.5 MHz fundamental crystal or clock input, the following four tables apply:
A Clocks Select Table (outputs in MHz) ASC1 0 0 0 1 1 1 ASC0 0 M 1 0 M 1 CLKA1 50 Test 37.5 16.6667 Test 33.3333 CLKA2 off (low) Test off (low) 8.3333 Test 16.6667 B Clocks Select Table (outputs in MHz) BSC1 0 0 0 1 1 1 BSC0 0 M 1 0 M 1 CLKB1 Test 33.3333 50 41.6667 Test 66.6667 CLKB2 Test 16.6667 25 20.8333 Test 33.3333
C Clocks Select Table (outputs in MHz) CCS 0 M 1 CLKC1 62.5 Test 37.5 CLKC2 62.5 Test 37.5
Reference Output Clock Frequency (in MHz) REFOUT 12.5
0 = connect directly to GND M = leave unconnected (automatically self biases to VDD/2) 1 = connect directly to VDD
MDS 650-27 D Integrated Circuit Systems, Inc.
3
525 Race Street, San Jose, CA 95126
Revision 070505 tel (408) 297-1201
www.icst.com
ICS650-27 Networking Clock Source
External Components
The ICS650-27 requires a minimum number of external components for proper operation.
Crystal Information
The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation: Crystal caps (pF) = (CL - 6) x 2 In the equation, CL is the crystal load capacitance. So, for a crystal with a 16pF load capacitance, two 20 pF [(16-6) x 2] capacitors should be used.
Decoupling Capacitor
Decoupling capacitors of 0.01F must be connected between each VDD and GND (pins 4 and 6, pins 16 and 14), as close to the device as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-27. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5 V to VDD+0.5 V -40 to +85C -65 to +150C 175C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
-40 +3.0
Typ.
+3.3
Max.
+85 +3.6
Units
C V
MDS 650-27 D Integrated Circuit Systems, Inc.
4
525 Race Street, San Jose, CA 95126
Revision 070505 tel (408) 297-1201
www.icst.com
ICS650-27 Networking Clock Source
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85C Parameter Operating Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage, CMOS level Operating Supply Current Short Circuit Current Internal pull-up resistor Nominal output impedance Symbol VDD VIH VIL VIH VIL VIH VIL VOH VOL VOH IDD IOS RPU ZOUT X1 pin only, CLK input X1 pin only, CLK input all tri-level type inputs all tri-level type inputs all other inputs all other inputs IOH = -25 mA IOL = 25mA IOH = -8 mA No Load Each output BCS1, OE pins ACSI pin VDD-0.4 50 50 510 120 20 2.4 0.8 2 0.8 VDD-0.5 0.5 Conditions Min. 3.0 VDD/2+1 Typ. 3.3 VDD/2 VDD/2 VDD/2-1 Max. 3.6 Units V V V V V V V V V V mA mA k k
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V10%, Ambient Temperature -40 to +85C
Parameter
Input Frequency Output Rise Time Output Fall Time Output Clock Duty Cycle Frequency Error Absolute Jitter, short term
Note 1: Measured with 15 pF load
Symbol
Conditions
Min.
10
Typ.
12.5 or 25
Max. Units
27 1.5 1.5 MHz ns ns % ppm ps
tOR tOF
0.8 to 2.0 V, Note 1 2.0 to 0.8 V, Note 1 At VDD/2, Note 1 All clocks Variation from mean, Note 1 150 40 50
60 0
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
135 93 78 60
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
JC
MDS 650-27 D Integrated Circuit Systems, Inc.
5
525 Race Street, San Jose, CA 95126
Revision 070505 tel (408) 297-1201
www.icst.com
ICS650-27 Networking Clock Source
Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
20
Millimeters Symbol Min Max
Inches Min Max
E1 INDEX AREA
E
12 D
A A1 A2 b C D E E1 e L
1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0 8
.053 .069 .0040 .010 -.059 0.008 0.012 .007 .010 .337 .344 .228 .244 .150 .157 0.025 Basic .016 .050 0 8
A2 A1
A
c
-Ce
b SEATING PLANE L
.10 (.004)
C
Ordering Information
Part / Order Number
ICS650R-27I ICS650R-27IT ICS650R-27ILF ICS650R-27ILFT
Marking
ICS650R-27I ICS650R-27I 650R-27ILF 650R-27ILF
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP
Temperature
-40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 650-27 D Integrated Circuit Systems, Inc.
6
525 Race Street, San Jose, CA 95126
Revision 070505 tel (408) 297-1201
www.icst.com

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